Yavuz, S., et al. (2024). Development of a 2-4 double arbiter PUF design on FPGA with enhanced performance.

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Title

Yavuz, S. (2024). Development of a 2-4 double arbiter PUF design on FPGA with enhanced performance.

Abstract

Implementation of delay-based Physical Unclonable Functions (PUFs) on FPGAs poses significant challenges due to high requirements, such as the generation of unique and reliable keys. These requirements must be fulfilled, especially when using PUFs in security applications, otherwise security cannot be guaranteed. In addition, it must be ensured that physical disturbances such as fluctuations in the ambient temperature do not have a major impact on the performance of the PUF and therefore on security. In this paper, the implementation and evaluation of a novel 56-bit 2-4 Double Arbiter PUF (DAPUF) is presented. For performance analysis, the proposed 2-4 DAPUF is investigated with 20 Digilent Nexys-3 (AMD-Xilinx Spartan-6 FPGA) boards and a large data set of 30 million challenges under varying ambient temperature in the range from 0°C to 50°C. Our experimental results show that the proposed 2-4 DAPUF is resistant to temperature fluctuations. Here, the maximum change in reliability amounts to 1.18%. For randomness and uniqueness, the changes are less than 0.50%. Furthermore, our results show that performance can be significantly improved by combining PUFs with XOR operations.